1. Field of the Invention
The present invention relates to power supply regulator circuits, and in particular, to power supply voltage regulator circuits particularly suitable for voltage-sensitive circuits such as voltage-controlled oscillators.
2. Description of the Related Art
In circuits for high speed data communications, the high frequency phase-locked loop (PLL) is a critical component and requires low jitter. For example, a physical layer performing according to the IEEE 1394A standard when outputting serial data at the rate of 400 megabytes per second requires extremely low jitter (less than 100 picoseconds) within its clock signal for encoding and decoding the data.
For integrated circuits using complementary metal oxide semiconductor (CMOS) technology, there are three major sources of jitter within the clock signal. The first source is variations in the power supply voltage which, in turn, cause variations in the operating frequency of the voltage-controlled oscillator (VCO). This is often a dominant source of long term jitter. Accordingly, it is important that both AC and DC power supply rejection be as high as possible.
A second source is transistor band-limited thermal noise in the VCO. Clock jitter can result from the tracking and suppressing by the PLL of the noise at frequencies within the PLL loop bandwidth.
A third source is dI/dt noise induced onto the power supply and ground lines due to current fluctuations caused by switching of the CMOS logic. This often appears as cycle-to-cycle, or multiple-cycle, accumulated short term clock jitter.
Referring to FIG. 1, a PLL with a VCO can be modeled in the s-domain with a functional block diagram as shown. As indicated, the output phase noise .theta.o is the result of the sum of effects of various sources of phase noise, including internal sources .theta.ni, .theta.no and an external source in the form of noise Vccn on the power supply voltage Vcc. This injected noise voltage Vccn is affected according to a transfer function identified as Hn(s), the output of which is added to the output voltage Vcnt from the loop filter Zf(s). This noise is then filtered by the voltage-to-phase band-pass characteristic Gbp(s). This is represented below in Equations 1, 2 and 3. ##EQU1##
If it is assumed that the external noise Vccn is dominant and the internal noise .theta.ni, .theta.no can be assumed negligible, i.e., equal to zero, this allows Equation 1 to be simplified to Equation 4 (with .theta.i=0). ##EQU2##
According to Equation 4, the zero at the origin (due to the factor "s" in the numerator of Equation 4) indicates that for slow variations in the injected noise voltage Vccn (as well as any variations in its associated transfer function Hn(s)), the output noise .theta.o is small. If, however, the rate of Vccn*Hn(s) increases, the gain of the VCO (kVCO/s) and, hence, the loop gain, decreases. This results in the loop error and, therefore, the loop noise, increasing. As the rate of change of Vccn*Hn(s) approaches .omega.z=(1+Cp/C)/RCp, the loop gain is reduced by the low-pass loop filter as well. This effect is represented by the transfer function zero at -(1+Cp/C)/RCp. Since (1+Cp/C) is determined by the loop bandwidth and its stability, the high frequency zero can be slightly increased by raising the value of the capacitor C. Therefore, reduction in the voltage supply noise must be achieved by some other technique.
Referring to FIG. 2, one conventional technique to reduce noise from the power supply voltage involves regulating the power supply voltage Vcc through a regulator circuit as shown. The VCO is a conventional ring oscillator composed of a selected number of inverters and is powered through a voltage-to-current converter in the form of a current mirror circuit M7, M8 powered by a regulated voltage source Vvco. This voltage Vvco is regulated by an operational amplifier (op amp) OTA driving a P-MOS transistor M5 amplifier, both of which are powered by the raw power supply voltage Vcc. The reference voltage Vref driving the op amp OTA determines the regulated voltage Vvco. A compensation capacitor C.sub.C provides frequency compensation for the amplifier M5. The output voltage Vf from a charge pump circuit (not shown) is filtered and drives an N-MOS transistor M6 amplifier and thereby determines the input current for the current mirror circuit M7, M8. A filter capacitor C.sub.L filters the regulated voltage Vvco.
Referring to FIG. 3, the op amp OTA is shown in more detail. As can be seen, since the combination of the op amp OTA and the amplifier M5 provide two gain stages for supplying the load current I.sub.L to the VCO, frequency compensation is required due to the unity gain configuration. In order to achieve a phase margin of 65.degree., the compensation capacitance C.sub.C must have a value which is at least 0.22 times the value of the filter capacitance C.sub.L. This requirement is illustrated below by Equations 5-10. Such a high relative value of capacitance for the compensation capacitor C.sub.C reduces the amount of power supply rejection available from such a circuit configuration. ##EQU3##